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tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 1 post office box 1443 ? houston, texas 772511443 single power supply supports 5 v 10% read/write operation organizatio n... 1048 576 by 8 bits array-blocking architecture one 16k-byte boot sector two 8k-byte parameter sectors one 32k-byte sector fifteen 64k-byte sectors any combination of sectors can be erased. supports full-chip erase any combination of sectors can be marked as read-only boot-code sector architecture t = top sector b = bottom sector sector protection hardware protection method that disables any combination of sectors from write or erase operations using standard programming equipment embedded program/erase algorithms automatically pre-programs and erases any sector automatically programs and verifies the program data at specified address jedec standards compatible with jedec byte pinouts compatible with jedec eeprom command set fully automated on-chip erase and program operations 100 000 program/erase cycles low power dissipation 40-ma typical active read for byte mode 60-ma typical program/erase current less than 100- m a standby current 5 m a in deep power-down mode all inputs/outputs ttl-compatible erase suspend/resume supports reading data from, or programming data to, a sector not being erased hardware-reset pin initializes the internal-state machine to the read operation 40-pin thin small-outline package (tsop) (dcd suffix) detection of program/erase operation data polling and toggle bit feature of program/erase cycle completion hardware method for detection of program/erase cycle completion through ready/busy (ry/by ) output pin high-speed data access at 5-v v cc 10% at three temperature ranges 80 ns commercia l...0 c to 70 c 90 ns commercia l...0 c to 70 c 100 ns extende d...40 c to 85 c 120 ns automotiv e...40 c to 125 c please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. product preview product preview information concerns products in the formative or design phase of development. characteristic data and other specifications are design goals. texas instruments reserves the right to change or discontinue these products without notice. copyright ? 1997, texas instruments incorporated a[0 :19] address inputs dq[0 :7] data in / data out ce chip enable oe output enable nc no internal connection reset reset / deep power down ry / by ready / busy output v cc power supply v ss ground we write enable pin nomenclature
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 2 post office box 1443 ? houston, texas 772511443 40-pin tsop dcd package ( top view ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a16 a15 a14 a13 a12 a11 a9 a8 we reset nc ry / by a18 a7 a6 a5 a4 a3 a2 a1 a17 v ss nc a19 a10 dq7 dq6 dq5 dq4 v cc v cc nc dq3 dq2 dq1 dq0 oe v ss ce a0 description the tms29f008t/b is an 1 048 576 by 8-bit (8 388 608-bit), 5-v single-supply, programmable read-only memory device that can be electrically erased and reprogrammed. this device is organized as 1 024k by 8 bits, divided into the following 19 sectors: one 16k-byte boot sector two 8k-byte sectors one 32k-byte sector fifteen 64k-byte sectors any combination of sectors can be marked as read-only or erased. full-chip erasure is also supported. sector data protection is afforded by methods that can disable any combination of sectors from write or read operations using standard programming equipment. an on-chip state machine provides an on-board algorithm that automatically pre-programs and erases any sector before it automatically programs and verifies program data at any specified address. the command set is compatible with the jedec 8m-bit electrically erasable, programmable read-only memory (eeprom) command set. a suspend/resume feature allows access to unaltered memory blocks during a section-erase operation. all outputs of this device are ttl-compatible. additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector that is not being erased. product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 3 post office box 1443 ? houston, texas 772511443 description (continued) device operations are selected by writing jedec-standard commands into the command register using standard microprocessor write timings. the command register acts as an input to an internal-state machine which interprets the commands, controls the erase and programming operations, outputs the status of the device, outputs the data stored in the device, and outputs the device algorithm-selection code. on initial power up, the device defaults to the read mode. a hardware-reset pin initializes the internal-state machine to the read operation. the device has low power dissipation with a 40-ma active read for the byte mode, 60-ma typical program/erase current mode, and less than 100- a standby current with a 5- a deep-power-down mode. these devices are offered with 80-, 90-, 100-, and 120-ns access times. table 1 and table 2 show the sector-address ranges. the tms29f008t/b is offered in a 40-pin thin small-outline package (tsop) (dcd suffix). device symbol nomenclature speed option 80 = 80 ns 90 = 90 ns 100 = 100 ns 120 = 120 ns boot code selection architecture t = top sector b = bottom sector device number / description 8m bits t 90 tms29f008 temperature range designator l = commercial (0 c to 70 c) e = extended ( 40 c to 85 c) q = automotive ( 40 c to 125 c) package designator dcd = 40-pin plastic dual small-outline package program/erase endurance c = 100 000 cycles b = 10 000 cycles cl dcd product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 4 post office box 1443 ? houston, texas 772511443 logic symbol 2 a 0 1048575 flash memory 1048576 8 0 g1 [pwr dwn] g2 1, 2 en (read) 1c3 (write) a, 3d ? 4 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 ry / by reset ce oe we dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 21 20 19 18 17 16 15 14 8 7 36 6 5 4 3 2 1 40 13 37 12 10 22 24 9 25 26 27 28 32 33 34 35 a, z4 19 2 this symbol is in accordance with ansi / ieee std 91-1984 and iec publication 617-12. product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 5 post office box 1443 ? houston, texas 772511443 block diagram ry / by buffer state control command registers erase voltage generator pgm voltage generator input/output buffers data latch y-decoder x-decoder a d d r e s s l a t c h y-gating chip-enable output-enable logic dq0 dq7 v cc v ss reset ce oe a0 a19 ry / by cell matrix v cc detector timer stb stb we product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 6 post office box 1443 ? houston, texas 772511443 operation see table 1 and table 2 for the sector-address ranges of the tms29f008t/b. table 1. top-boot sector-address ranges 2 a19 a18 a17 a16 a15 a14 a13 sector size address range sa18 1 1 1 1 1 1 x 16k byte fc000h fffffh sa17 1 1 1 1 1 0 1 8k byte fa000h fbfffh sa16 1 1 1 1 1 0 0 8k byte f8000h f9fffh sa15 1 1 1 1 0 x x 32k byte f0000h f7fffh sa14 1 1 1 0 x x x 64k byte e0000h effffh sa13 1 1 0 1 x x x 64k byte d0000h dffffh sa12 1 1 0 0 x x x 64k byte c0000h cffffh sa11 1 0 1 1 x x x 64k byte b0000h bffffh sa10 1 0 1 0 x x x 64k byte a0000h affffh sa9 1 0 0 1 x x x 64k byte 90000h 9ffffh sa8 1 0 0 0 x x x 64k byte 80000h 8ffffh sa7 0 1 1 1 x x x 64k byte 70000h 7ffffh sa6 0 1 1 0 x x x 64k byte 60000h 6ffffh sa5 0 1 0 1 x x x 64k byte 50000h 5ffffh sa4 0 1 0 0 x x x 64k byte 40000h 4ffffh sa3 0 0 1 1 x x x 64k byte 30000h 3ffffh sa2 0 0 1 0 x x x 64k byte 20000h 2ffffh sa1 0 0 0 1 x x x 64k byte 10000h 1ffffh sa0 0 0 0 0 x x x 64k byte 00000h 0ffffh 2 the address range is a0a19 product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 7 post office box 1443 ? houston, texas 772511443 operation (continued) table 2. bottom-boot sector-address ranges 2 a19 a18 a17 a16 a15 a14 a13 sector size address range sa18 1 1 1 1 x x x 64k byte f0000h fffffh sa17 1 1 1 0 x x x 64k byte e0000h effffh sa16 1 1 0 1 x x x 64k byte d0000h dffffh sa15 1 1 0 0 x x x 64k byte c0000h cffffh sa14 1 0 1 1 x x x 64k byte b0000h bffffh sa13 1 0 1 0 x x x 64k byte a0000h affffh sa12 1 0 0 1 x x x 64k byte 90000h 9ffffh sa11 1 0 0 0 x x x 64k byte 80000h 8ffffh sa10 0 1 1 1 x x x 64k byte 70000h 7ffffh sa9 0 1 1 0 x x x 64k byte 60000h 6ffffh sa8 0 1 0 1 x x x 64k byte 50000h 5ffffh sa7 0 1 0 0 x x x 64k byte 40000h 4ffffh sa6 0 0 1 1 x x x 64k byte 30000h 3ffffh sa5 0 0 1 0 x x x 64k byte 20000h 2ffffh sa4 0 0 0 1 x x x 64k byte 10000h 1ffffh sa3 0 0 0 0 1 x x 32k byte 08000h 0ffffh sa2 0 0 0 0 0 1 1 8k byte 06000h 07fffh sa1 0 0 0 0 0 1 0 8k byte 04000h 05fffh sa0 0 0 0 0 0 0 x 16k byte 00000h 03fffh 2 the address range is a0a19 product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 8 post office box 1443 ? houston, texas 772511443 operation (continued) see table 3 for the operation modes of the tms29f008t/b. table 3. operation modes mode functions 2 mode ce oe we a0 a1 a6 a9 reset dq0dq7 algorithm-selection mode v il v il v ih v il v il v il v id v ih manufacture-equivalent code 01h (tms29f008-byte) 5v p ower su pp ly v il v il v ih v ih v il v il v id v ih device-equivalent code d6h (tms29f008t-byte) 5 - v po w er s u ppl y v il v il v ih v ih v il v il v id v ih device-equivalent code 58h (tms29f008b-byte) read v il v il v ih a0 a1 a6 a9 v ih data out output disable v il v ih v ih x x x x v ih hi-z standby and write inhibit v ih x x x x x x v ih hi-z write 3 v il v ih v il a0 a1 a6 a9 v ih data in temporary sector unprotect x x x x x x x v id x verify sector protect v il v il v ih v il v ih v il v id v ih data out hardware reset x x x x x x x v il hi-z legend: v il = logic low v ih = logic high v id = 12.0 0.5 v 2 x can be v il or v ih . 3 see table 5 for valid address and data during write. read mode a logic-low signal applied to the ce and oe pins allows the output of the tms29f008t/b to be read. when two or more '29f008t/b devices are connected in parallel, the output of any one device can be read without interference. the ce pin is for power control and must be used for device selection. the oe pin is for output control, used to gate the data output onto the bus from the selected device. the address-access time (t avqv ) is the delay from stable address to valid output data. the chip-enable (ce ) access time (t elqv ) is the delay from ce low and stable addresses to valid output data. the output-enable access time (t glqv ) is the delay from oe low to valid output data when ce equals logic low and addresses are stable for at least the duration of t avqv t glqv . standby mode i cc supply current is reduced by applying a logic-high level on ce and reset to enter the standby mode. in the standby mode, the outputs are placed in the high-impedance state. applying a cmos logic-high level on ce and reset reduces the current to 100 m a. applying a ttl logic-high level on ce and reset reduces the current to 1 ma. if the '29f008t/b is deselected during erasure or programming, the device continues to draw active current until the operation is complete. output disable when oe equals v ih or ce equals v ih , output from the device is disabled and the output pins (dq0dq7) are placed in the high-impedance state. product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 9 post office box 1443 ? houston, texas 772511443 automatic-sleep mode the '29f008 has a built-in feature called automatic-sleep mode to minimize device energy consumption which is independent of ce , we , and oe , and is enabled when addresses remain stable for 300 ns. typical sleep-mode current is 100 m a. sleep mode does not affect output data, which remains latched and available to the system. algorithm selection the algorithm-selection mode provides access to a binary code that matches the device with its proper programming and erase command operations. this mode is activated when v id (11.5 v to 12.5 v) is placed on address pin a9. address pins a1 and a6 must be logic low. two bytes of code are accessed by toggling address pin a0 from v il to v ih . address pins other than a0, a1, and a6 can be at logic low or at logic high. the algorithm-selection mode can also be read by using the command register, which is useful when v id is not available to be placed on address pin a9. table 4 shows the binary algorithm-selection codes. table 4. algorithm-selection codes (5-v single power supply) 2 code dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 manufacturer-equivalent code 01h 0 0 0 0 0 0 0 1 tms29f008t-byte d6h 1 1 0 1 0 1 1 0 tms29f008b-byte 58h 0 1 0 1 1 0 0 0 sector protection 01h 0 0 0 0 0 0 0 1 2 a1 = v il , a6 = v il , ce = oe = v il erasure and programming erasure and programming of the '29f008 are accomplished by writing a sequence of commands using standard microprocessor write timing. the commands are written to a command register and input to the command-state machine (csm). the csm interprets the command entered and initiates program, erase, suspend, and resume operations as instructed. the csm acts as the interface between the write-state machine (wsm) and external-chip operations. the wsm controls all voltage generation, pulse generation, preconditioning, and verification of memory contents. program and block-/chip-erase functions are fully automatic. once the end of a program or erase operation has been reached, the device resets internally to the read mode. if v cc drops below the low-voltage-detect level (v lko ), any programming or erase operation is aborted and subsequent writes are ignored until the v cc level is greater than v lko . the control pins must be logically correct to prevent unintentional command writes or programming or erasing. command definitions device operating modes are selected by writing specific address and data sequences into the command register. table 5 defines the valid command sequences. writing incorrect address and data values or writing them in the incorrect sequence causes the device to reset to the read mode. the command register does not occupy an addressable memory location. the register is used to store the command sequence, along with the address and data needed by the memory array. commands are written by setting ce = v il , oe = v ih , and bringing we from logic high to logic low. addresses are latched on the falling edge of we and data is latched on the rising edge of we . holding we = v il and toggling ce is an alternative method. see the switching characteristics of the write/erase/program-operations section for specific timing information. product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 10 post office box 1443 ? houston, texas 772511443 command definitions (continued) table 5. command definitions command bus 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle command cycles addr data addr data addr data addr data addr data addr data read/reset 1 xxxh f0h read/reset 3 555h aah 2aah 55h 555h f0h ra rd al g orithm 3 555h aah 2aah 55h 555h 90h 01h d6h t go selection 3 555h aah 2aah 55h 555h 90h 01h 58h b program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector-erase suspend 1 xxxh b0h erase-suspend valid during sector-erase operation sector-erase resume 1 xxxh 30h erase-resume valid only after erase-suspend legend: ra = address of the location to be read pa = address of the location to be programmed sa = address of the sector to be erased addresses a13a19 select 1 to 19 sectors. rd = data to be read at selected address location pd = data to be programmed at selected address location read/reset command the read or reset mode is activated by writing either of the two read/reset command sequences into the command register. the device remains in this mode until another valid command sequence is input in the command register. memory data is available in the read mode and can be read with standard microprocessor read-cycle timing. on power up, the device defaults to the read/reset mode. a read/reset command sequence is not required and memory data is available. algorithm-selection command the algorithm-selection command allows access to a binary code that matches the device with the proper programming and erase command operations. after writing the three-bus-cycle command sequence, the first byte of the algorithm-selection code can be read from address xx00h. the second byte of the code can be read from address xx01h (see table 5). this mode remains in effect until another valid command sequence is written to the device. byte-program command programming is a four-bus-cycle command sequence. the first three bus cycles put the device into the program-setup state. the fourth bus cycle loads the address location and the data to be programmed into the device. the addresses are latched on the falling edge of we and the data is latched on the rising edge of we in the fourth bus cycle. the rising edge of we starts the program operation. the embedded programming function automatically provides needed voltage and timing to program and verify the cell margin. any further commands written to the device during the program operation are ignored. product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 11 post office box 1443 ? houston, texas 772511443 byte-program command (continued) programming can be performed at any address location in any sequence. when erased, all bits are in a logic-high state. logic lows are programmed into the device and only an erase operation can change bits from logic lows to logic highs. attempting to program a 1 into a bit that has been programmed previously to a 0 causes the internal-pulse counter to exceed the pulse-count limit, which sets the exceed-time-limit indicator (dq5) to a logic-high state. the automatic-programming operation is complete when the data on dq7 is equivalent to the data written to this bit, at which time the device returns to the read mode and addresses are no longer latched. figure 8 shows a flowchart of the typical device-programming operation. chip-erase command chip erase is a six-bus-cycle command sequence. the first three bus cycles put the device into the erase-setup state. the next two bus cycles unlock the erase mode. the sixth bus cycle loads the chip-erase command. this command sequence is required to ensure that the memory contents are not erased accidentally. the rising edge of we starts the chip-erase operation. any further commands written to the device during the chip-erase operation are ignored. the embedded chip-erase function automatically provides voltage and timing needed to program and to verify all the memory cells prior to electrical erase. it then erases and verifies the cell margin automatically without programming the memory cells prior to erase. figure 10 shows a flowchart of the typical chip-erase operation. sector-erase command sector-erase is a six-bus-cycle command sequence. the first three bus cycles put the device into the erase-setup state. the next two bus cycles unlock the erase mode and then the sixth bus cycle loads the sector-erase command and the sector-address location to be erased. any address location within the desired sector can be used. the addresses are latched on the falling edge of we and the sector-erase command (30h) is latched on the rising edge of we in the sixth bus cycle. after a delay of 80 m s from the rising edge of we , the sector-erase operation begins on the selected sector(s). additional sectors can be selected to be erased concurrently during the sector-erase command sequence. for each additional sector to be selected for erase, another bus cycle is issued. the bus cycle loads the next sector-address location and the sector-erase command. the time between the end of the previous bus cycle and the start of the next bus cycle must be less than 100 m s; otherwise, the new sector location is not loaded. a time delay of 100 m s from the rising edge of the last we starts the sector-erase operation. if there is a falling edge of we within the 100 m s time delay, the timer is reset. one to nineteen sector-address locations can be loaded in any sequence. the state of the delay timer can be monitored using the sector-erase delay indicator (dq3). if dq3 is at logic low, the time delay has not expired. see the operation status section for a description. any command other than erase suspend (b0h) or sector erase (30h) written to the device during the sector-erase operation causes the device to exit the sector-erase mode and the contents of the sector(s) selected for erase are no longer valid. to complete the sector-erase operation, re-issue the sector-erase command sequence. the embedded sector-erase function automatically provides needed voltage and timing to program and to verify all of the memory cells prior to electrical erase and then erases and verifies the cell margin automatically. programming the memory cells prior to erase is not required. see the operation status section for a full description. figure 12 shows a flowchart of the typical sector-erase operation. product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 12 post office box 1443 ? houston, texas 772511443 erase-suspend command the erase-suspend command (b0h) allows interruption of a sector-erase operation to read data from unaltered sectors of the device. erase-suspend is a one-bus-cycle command. the addresses can be v il or v ih and the erase-suspend command (b0h) is latched on the rising edge of we . once the sector-erase operation is in progress, the erase-suspend command requests the internal write-state machine to halt operation at predetermined breakpoints. the erase-suspend command is valid only during the sector-erase operation and is invalid during programming and chip-erase operations. the sector-erase delay timer expires immediately if the erase-suspend command is issued while the delay is active. after the erase-suspend command is issued, the device takes between 0.1 m s and 15 m s to suspend the operation. the toggle bit must be monitored to determine when the suspend has been executed. when the toggle bit stops toggling, data can be read from sectors that are not selected for erase. reading from a sector selected for erase can result in invalid data. see the operation status section for a full description. once the sector-erase operation is suspended, reading from or programming to a sector that is not being erased can be performed. this command is applicable only during sector-erase operation. any other command written during erase-suspend mode to the suspended sector is ignored. erase-resume command the erase-resume command (30h) restarts a suspended sector-erase operation from the point where it was halted. erase resume is a one-bus-cycle command. the addresses can be v il or v ih and the erase-resume command (30h) is latched on the rising edge of we . when an erase-suspend/erase-resume command combination is written, the internal-pulse counter (exceed timing limit) is reset. the erase-resume command is valid only in the erase-suspend state. after the erase-resume command is executed, the device returns to the valid sector-erase state and further writes of the erase-resume command are ignored. after the device has resumed the sector-erase operation, another erase-suspend command can be issued to the device. operation status the status of the device during an automatic-programming algorithm, chip-erase, or automatic-erase algorithm can be determined in three ways: dq7: data polling dq6: toggle bit ry / by : ready / busy bit status-bit definitions during operation of the automatic embedded program and erase functions, the status of the device can be determined by reading the data state of designated outputs. the data-polling bit (dq7) and toggle bit (dq6) require multiple successive reads to observe a change in the state of the designated output. table 6 defines the values of the status flags. product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 13 post office box 1443 ? houston, texas 772511443 status-bit definitions (continued) table 6. operation status flags 2 device operation 3 dq7 dq6 dq5 dq3 dq2 ry/by programming dq7 t 0 0 no tog 0 program/erase in auto-erase 0 t 0 1 0 in progress erase sus p end mode erase-sector address 1 no tog 0 0 t 1 erase - s u spend mode non-erase sector address d d d d d 1 program in erase suspend dq7 ? t 0 0 1 0 programming dq7 t 1 0 no tog 0 exceeded time limits program/erase in auto erase 0 t 1 1 # 0 program in erase suspend dq7 t 1 0 no tog 0 successful operation programming complete d d d d d 1 complete sector-/chip-erase complete 1 1 1 1 1 1 2 t= toggle, d= data, no tog= no toggle 3 dq4, dq1, dq0 are reserved for future use. dq2 can be toggled when the sector address applied is an erasing sector. dq2 cannot be toggled when the sector address applied is a non-erasing sector. dq2 is used to determine which sectors are erasing and which are not. ? status flags apply when outputs are read from the address of a non-erase-suspend operation. # if dq5 is high (exceeded timing limits), successive reads from a problem sector causes dq2 to toggle. data-polling (dq7) the data-polling-status function outputs the complement of the data latched into the dq7 data register while the write-state machine is engaged in a program or erase operation. data bit dq7 changes from complement to true to indicate the end of an operation. data-polling is available only during programming, chip-erase, sector-erase, and sector-erase-timing delay. data-polling is valid after the rising edge of we in the last bus cycle of the command sequence loaded into the command register. figure 14 shows a flowchart for data-polling. during a program operation, reading dq7 outputs the complement of the dq7 data to be programmed at the selected address location. upon completion, reading dq7 outputs the true dq7 data loaded into the program-data register. during the erase operations, reading dq7 outputs a logic low. upon completion, reading dq7 outputs a logic high. also, data-polling must be performed at a sector address that is within a sector that is being erased. otherwise, the status is invalid. when using data-polling, the address should remain stable throughout the operation. during a data-polling read, while oe is logic low, data bit dq7 can change asynchronously. depending on the read timing, the system can read valid data on dq7, while other dq pins are still invalid. a subsequent read of the device is valid. see figure 15 for the data-polling timing diagram. toggle bit (dq6) the toggle-bit status function outputs data on dq6, which toggles between logic high and logic low while the write-state machine is engaged in a program or erase operation. when dq6 stops toggling after two consecutive reads to the same address, the operation is complete. the toggle bit is available only during programming, chip erase, sector erase, and sector-erase-timing delay. toggle-bit data is valid after the rising edge of we in the last bus cycle of the command sequence loaded into the command register. figure 16 shows a flowchart of the toggle-bit status-read algorithm. depending on the read timing, dq6 can stop toggling while other dq pins are still invalid and a subsequent read of the device is valid. see figure 17 for the toggle-bit timing diagram. product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 14 post office box 1443 ? houston, texas 772511443 exceed time limit (dq5) program and erase operations use an internal-pulse counter to limit the number of pulses applied. if the pulse-count limit is exceeded, dq5 is set to a logic-high data state. this indicates that the program or erase operation has failed. dq7 does not change from complemented data to true data and dq6 does not stop toggling when read. to continue operation, the device must be reset. the exceed-time-limit condition occurs when attempting to program a logic-high state into a bit that has been programmed previously to a logic low. only an erase operation can change bits from logic low to logic high. after reset, the device is functional and can be erased and reprogrammed. sector-load-timer (dq3) the sector-load-timer status bit, dq3, is used to determine whether the time to load additional sector addresses has expired. after completion of a sector-erase command sequence, dq3 remains at a logic low for 100 m s. this indicates that another sector-erase command sequence can be issued. if dq3 is at a logic high, it indicates that the delay has expired and attempts to issue additional sector-erase commands are ignored. see the sector-erase command section for a description. the data-polling and toggle bit are valid during the 100- m s time delay and can be used to determine if a valid sector-erase command has been issued. to ensure additional sector-erase commands have been accepted, the status of dq3 should be read before and after each additional sector-erase command. if dq3 is at a logic low on both reads, the additional sector-erase command was accepted. toggle bit 2 (dq2) the state of dq2 determines whether the device is in algorithmic-erase mode or erase-suspend mode. dq2 toggles if successive reads are issued to the erasing or erase-suspended sector, assuming in case of the latter that the device is in erase-suspend-read mode. it also toggles when dq5 becomes a logic high due to the timer-exceed limit, and reads are issued to the failed sector. dq2 does not toggle in any other sector due to dq5 failure. when the device is in erase-suspend-program mode, successive reads from the non-erase-suspended sector causes a logic high on dq2. ready/ busy bit (ry/ by ) the ry/ by bit indicates when the device can accept new commands after performing algorithmic operations. if the ry/ by (open-drain output) bit is low, the device is busy with either a program or erase operation and does not accept any other commands except for erase suspend. while it is in the erase-suspend mode, ry/ by remains high. in program mode, the ry/ by bit is valid (logic low) after the fourth we pulse. in erase mode, it is valid after the sixth we pulse. there is a delay period t busy , after which the ry/ by bit becomes valid. see figure 24 for the timing waveform. since the ry/ by bit is an open-drain output, several such bits can be combined in parallel with a pullup resistor to v cc . hardware-reset bit (reset ) when the reset pin is driven to a logic low, it forces the device out of the currently active mode and into a reset state. it also avoids bus contention by placing the outputs into the high-impedance state for the duration of the reset pulse. during program or erase operation, if reset is asserted to logic low, the ry/ by bit remains at logic low until the reset operation is complete. since this can take anywhere from 1 m s to 20 m s, the ry/ by bit can be used to sense reset completion or the user can allow a maximum of 20 m s. if reset is asserted during read mode, then the reset operation is complete within 500 ns. see figure 1 and figure 2 for timing specifications. the reset pin also can be used to drive the device into deep power-down (standby) mode by applying v ss 0.3 v to it. i cc4 reads <1 m a typical, and 5 m a maximum for cmos inputs. standby mode can be entered anytime, regardless of the condition of ce . product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 15 post office box 1443 ? houston, texas 772511443 hardware-reset bit (reset ) (continued) asserting reset during program or erase can leave erroneous data in the address locations. these locations need to be updated after the device resumes normal operations. a minimum of 50 ns must be allowed after reset goes high before a valid read can take place. reset ry/by t rl = 500 ns 20 m s max figure 1. device reset during a program or erase operation t rl = 500 ns reset ry/by 0 v figure 2. device reset during read mode temporary hardware-sector unprotect feature this feature temporarily enables both programming and erase operations on any combination of one to nineteen sectors that were previously protected. this feature is enabled using high voltage v id (11.5 v to 12.5 v) on the reset pin, using standard command sequences. normally, the device is delivered with all sectors unprotected. sector-protect programming the sector-protect programming mode is activated when a6, a0, and ce are at v il , and address pin a9 and control pin oe are forced to v id . address pin a1 is set to v ih .the sector-select address pins a13a19 are used to select the sector to be protected. address pins a0a12 and i/o pins must be stable and can be either v il or v ih . once the addresses are stable, we is pulsed low for 100 m s, causing programming to begin on the falling edge of we and to terminate on the rising edge of we . figure 18 is a flowchart of the sector-protect algorithm, and figure 19 shows a timing diagram of the sector-protect operation. commands to program or erase a protected sector do not change the data contained in the sector. attempts to program and erase a protected sector cause the data-polling bit (dq7) and the toggle bit (dq6) to operate from 2 m s to 100 m s and then return to valid data. product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 16 post office box 1443 ? houston, texas 772511443 sector-protect verify verification of the sector-protection programming is activated when we = v ih , oe = v il , ce = v il , and address pin a9 = v id . address pins a0 and a6 are set to v il , and a1 is set to v ih . the sector-address pins a13a19 select the sector that is to be verified. the other addresses can be v ih or v il . if the sector that was selected is protected, the dqs output 01h. if the sector is not protected, the dqs output 00h. sector-protect verify can also be read using the algorithm-selection command. after issuing the three-bus-cycle command sequence, the sector-protection status can be read on dq0. set address pins a0 = v il , a1 = v ih , and a6 = v il , and then the sector address pins a13a19 select the sector to be verified. the remaining addresses are set to v il . if the sector selected is protected, dq0 outputs a logic-high state. if the sector selected is not protected, dq0 outputs a logic-low state. this mode remains in effect until another valid command sequence is written to the device. figure 18 is a flowchart of the sector-protect algorithm and figure 19 shows a timing diagram of the sector-protect operation. sector unprotect prior to sector unprotect, all sectors must be protected using the sector-protect programming mode. the sector unprotect is activated when address pin a9 and control pin oe are forced to v id . address pins a1 and a6 are set to v ih while ce and a0 are set to v il . the sector-select address pins a13a19 can be v il or v ih . all sectors are unprotected in parallel and once the inputs are stable, we is pulsed low for 10 ms, causing the unprotect operation to begin on the falling edge of we and to terminate on the rising edge of we . figure 20 is a flowchart of the sector-unprotect algorithm and figure 21 shows a timing diagram of the sector-unprotect operation. sector-unprotect verify verification of the sector unprotect is accomplished when we = v ih , oe = v il , ce =v il and address pin a9 = v id , and then select the sector to be verified. address pins a1 and a6 are set to v ih , and a0 is set to v il . the other addresses can be v ih or v il . if the sector selected is protected, the dqs output 01h. if the sector is not protected, the dqs output 00h. sector unprotect can also be read using the algorithm-selection command. low v cc write lockout during power-up and power-down operations, write cycles are locked out for v cc less than v lko . if v cc < v lko , the command input is disabled and the device is reset to the read mode. on power up, if ce = v il , we = v il , and oe = v ih , the device does not accept commands on the rising edge of we . the device automatically powers up in the read mode. glitching pulses of less than 5 ns (typical) on oe , we , or ce do not issue a write cycle. power supply considerations each device should have a 0.1- m f ceramic capacitor connected between v cc and v ss to suppress circuit noise. printed circuit traces to v cc should be appropriate to handle the current demand and minimize inductance. product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 17 post office box 1443 ? houston, texas 772511443 absolute maximum ratings over ambient temperature range (unless otherwise noted) 2 supply voltage range, v cc (see note 1) 0.6 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range: all inputs except a9, ce , oe (see note 2) 0.6 v to v cc + 1 v . . . . . . . . . . . . . . . . . . . . a9, ce , oe 0.6 v to 13.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range (see note 3) 0.6 v to v cc + 1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ambient temperature range during read / erase / program, t a (l) 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (e) 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (q) 40 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. all voltage values are with respect to v ss . 2. the voltage on any input pin can undershoot to 2 v for periods less than 20 ns (see figure 4). 3. the voltage on any input or output pin can overshoot to 7 v for periods less than 20 ns (see figure 5). recommended operating conditions min max unit v cc supply voltage 4.5 5.5 v v ih high level dc in p ut voltage ttl 2 v cc +0.5 v v ih high - le v el dc inp u t v oltage cmos 0.7 * v cc v cc +0.5 v v il low level dc in p ut voltage ttl 0.5 0.8 v v il lo w- le v el dc inp u t v oltage cmos 0.5 0.8 v v id algorithm-selection and sector-protect input voltage 11.5 12.5 v v lko low v cc lock-out voltage 3.2 4.2 v l version 0 70 t a ambient temperature e version 40 85 c q version 40 125 product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 18 post office box 1443 ? houston, texas 772511443 electrical characteristics over recommended ranges of supply voltage and ambient temperature parameter test conditions min max unit ttl-input level v cc = v cc min, i oh = 2.5 ma 2.4 v v oh high-level output voltage cmos-input level v cc = v cc min, i oh = 100 m a v cc 0.4 v cmos-input level v cc = v cc min, i oh = 2.5 ma 0.85 * v cc v ol low-level output voltage v cc = v cc min, i ol = 5.8 ma 0.45 v i i input current (leakage) v cc = v cc max, v in = v ss to v cc 1 m a i o output current (leakage) v o = v ss to v cc ,ce = v ih 1 m a i id high-voltage current (standby) a9 or ce or oe = v id max 35 m a i cc1 v cc su pp ly current (standby) ttl-input level ce = v ih , v cc = v cc max 1 ma i cc1 v cc s u ppl y c u rrent (standb y ) cmos-input level ce = v cc 0.2, v cc = v cc max 100 m a i cc2 v cc supply current (see notes 4 and 5) ce = v il ,oe = v ih 40 ma i cc3 v cc supply current (see note 6) ce = v il ,oe = v ih 60 ma i cc4 v cc supply current (standby during reset) v cc = v cc max, reset = v ss 0.3 v 5 m a i cc5 automatic sleep mode (see notes 5 and 7) v ih = v cc 0.3 v, v il = v ss 0.3 v 100 m a notes: 4. i cc current in the read mode, switching at 6 mhz 5. i out = 0 ma 6. i cc current while erase or program operation is in progress 7. automatic sleep mode is entered when addresses remain stable for 300 ns. capacitance over recommended ranges of supply voltage and ambient temperature parameter test conditions min max unit c i1 input capacitance (all inputs except a9, ce , oe ) v i = 0 v, f = 1 mhz 7.5 pf c i2 input capacitance (a9, ce , oe ) v i = 0 v, f = 1 mhz 9 pf c o output capacitance v o = 0 v, f = 1 mhz 12 pf product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 19 post office box 1443 ? houston, texas 772511443 parameter measurement information i ol i oh output under test 0.5 ma 0.5 ma c l = 30 pf 1.5 v (see note a and note b) 2.4 v 0.45 v 0.8 v 2.0 v notes: a. c l includes probe and fixture capacitance. b. the ac testing inputs are driven at 2.4 v for logic high and 0.45 v for logic low. timing measurements are made at 2 v for lo gic high and 0.8 v for logic low on both inputs and outputs. each device should have a 0.1- m f ceramic capacitor connected between v cc and v ss as closely as possible to the device pins. figure 3. ac test output load circuit 2.0 v 0.5 v +0.8 v 20 ns 20 ns 20 ns figure 4. maximum negative overshoot waveform v cc + 2.0 v v cc + 0.5 v 2.0 v 20 ns 20 ns 20 ns figure 5. maximum positive overshoot waveform product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 20 post office box 1443 ? houston, texas 772511443 parameter measurement information switching characteristics over recommended ranges of supply voltage and ambient temperature, read-only operation parameter alternate '29f008-80 '29f008-90 '29f008-100 '29f008-120 unit parameter symbol min max min max min max min max unit t c(r) cycle time, read t avav 80 90 100 120 ns t a(a) access time, address t avqv 80 90 100 120 ns t a(e) access time, ce t elqv 80 90 100 120 ns t a(g) access time, oe t glqv 40 45 50 55 ns t dis(e) disable time, ce to high impedance t ehqz 30 30 30 40 ns t dis(g) disable time, oe to high impedance t ghqz 30 30 30 40 ns t en(e) enable time, ce to low impedance t elqx 0 0 0 0 ns t en(g) enable time, oe to low impedance t glqx 0 0 0 0 ns t h(d) hold time, output from address ce or oe change t axqx 0 0 0 0 ns product preview
tms29f008t, tms29f008b 1 048 576 by 8-bit flash memories smjs845a march 1997 revised october 1997 post office box 1443 houston, texas 772511443 ? 21 switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by we parameter alternate '29f008-80 '29f008-90 '29f008-100 '29f008-120 unit parameter symbol min typ max min typ max min typ max min typ max unit t c(w) cycle time, write t avav 80 90 100 120 ns t su(a) setup time, address t avwl 0 0 0 0 ns t h(a) hold time, address t wlax 45 50 50 65 ns t su(d) setup time, data t dvwh 45 50 50 65 ns t h(d) hold time, data valid after we high t whdx 0 0 0 0 ns t su(e) setup time, ce t elwl 0 0 0 0 ns t h(e) hold time, ce t ehwh 0 0 0 0 ns t w(wl) pulse duration, we low t wlwh1 45 50 50 65 ns t w(wh) pulse duration, we high t whwl 20 30 30 35 ns t rec(r) recovery time, read before write t ghwl 0 0 0 0 ns hold time, oe read t whgl1 0 0 0 0 ns hold time, oe toggle, data t whgl2 10 10 10 10 ns setup time, v cc t vcel 50 50 50 50 m s transition time, v id (see notes 8 and 9) t hvt 4 4 4 4 m s pulse duration, we low (see note 8) t wlwh2 100 100 100 100 m s pulse duration, we low (see note 9) t wlwh3 10 10 10 10 ms setup time, ce v id to we (see note 9) t ehvwl 4 4 4 4 m s setup time, oe v id to we (see notes 8 and 9) t ghvwl 4 4 4 4 m s t c(w)pr cycle time, programming operation t whwh1 8 8 8 8 m s write recovery time from ry / by t rb 0 0 0 0 ns notes: 8. sector-protect timing 9. sector-unprotect timing product preview
tms29f008t, tms29f008b 1 048 576 by 8-bit flash memories smjs845a march 1997 revised october 1997 t emp l ate r e l ease d ate: 7 11 94 22 post office box 1443 houston, texas 772511443 ? switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by we (continued) parameter alternate '29f008-80 '29f008-90 '29f008-100 '29f008-120 unit parameter symbol min typ max min typ max min typ max min typ max unit reset low time t rl 500 500 500 500 ns reset high time before read t rh 50 50 50 50 ns reset to power-down time t rpd 20 20 20 20 m s program/erase valid to ry / by delay t busy 90 90 90 90 ns t c(w)er cycle time, sector-erase operation t whwh2 1 1 1 1 s cycle time, chip-erase operation t whwh3 6 50 6 50 6 50 6 50 s notes: 8. sector-protect timing 9. sector -unprotect timing product preview
tms29f008t, tms29f008b 1 048 576 by 8-bit flash memories smjs845a march 1997 revised october 1997 post office box 1443 houston, texas 772511443 ? 23 switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by ce parameter alternate '29f008-80 '29f008-90 '29f008-100 '29f008-120 unit parameter symbol min typ max min typ max min typ max min typ max unit t c(w) cycle time, write t avav 80 90 100 120 ns t su(a) setup time, address t ave l 0 0 0 0 ns t h(a) hold time, address t elax 45 50 50 65 ns t su(d) setup time, data t dveh 45 50 50 65 ns t h(d) hold time, data t ehdx 0 0 0 0 ns t su(w) setup time, we t wlel 0 0 0 0 ns t h(w) hold time, we t ehwh 0 0 0 0 ns t w(el) pulse duration, ce low t eleh1 45 50 50 65 ns t w(eh) pulse duration, ce high t ehel 20 30 30 35 ns t rec(r) recovery time, read before write t ghel 0 0 0 0 ns setup time, oe t glel 0 0 0 0 ns t h(c) hold time, oe read t ehgl1 0 0 0 0 ns hold time, oe toggle, data t ehgl2 10 10 10 10 ns programming operation t eheh1 8 8 8 8 m s cycle time, sector-erase operation t eheh2 1 1 1 1 s cycle time, chip-erase operation t eheh3 6 50 6 50 6 50 6 50 s product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 24 post office box 1443 ? houston, texas 772511443 erase and program performance 2 parameter test conditions min typ max unit sector-erase time excludes 00h programming prior to erasure 1 3 15 s program word time excludes system-level overhead 9 11 5200 m s program time excludes system-level overhead 9 9 3 600 m s chip-programming time excludes system-level overhead 6 3 50 s erase/program cycles 100 000 1 000 000 cycles 2 the internal algorithms allow for 2.5-ms byte-program time. dq5 = 1 only after a byte takes the theoretical maximum time to pro gram. a minimal number of bytes can require signficantly more programming pulses than the typical byte. the majority of the bytes program withi n one or two pulses. this is demonstrated by the typical and maximum programming times listed above. 3 25 c, 5-v v cc , 100 000 cycles, typical pattern under worst-case conditions: 90 c, 5-v v cc , and 100 000 cycles latchup characteristics (see note 10) parameter min max unit input voltage with respect to v ss on all pins except i/o pins (including a9 and oe ) 1 13 v input voltage with respect to v ss on all i/o pins 1 v cc + 1 v current 100 100 ma note 10: includes all pins except v cc test conditions: v cc = 5 v, one pin at a time pin capacitance, all packages (see note 11) parameter test conditions typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 8 10 pf note 11: test conditions t a : 25 c, f = 1 mhz data retention parameter test conditions min max unit minimum p attern data retention time 150 c 10 years minim u m pattern data retention time 125 c 20 years product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 25 post office box 1443 ? houston, texas 772511443 read operation valid data dq we oe ce addresses valid addresses t axqx t ghqz t ehqz t elqx t glqx t glqv t elqv t avqv t avav figure 6. ac waveform for read operation product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 26 post office box 1443 ? houston, texas 772511443 write operation start next address yes no yes no write bus cycle program address / program data poll device status operation complete ? last address ? write bus cycle 555h / a0h write bus cycle 2aah / 55h write bus cycle 555h / aah end figure 7. program algorithm product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 27 post office box 1443 ? houston, texas 772511443 write operation (continued) dout dq7 pd a0h 55h aah dq we oe ce pa pa 555h 2aah 555h addresses t whdx t dvwh t whwl t ghwl t wheh t elwl t wlax t avwl t whwh1 t wlwh1 t avav notes: a. pa = address to be programmed b. pd = data to be programmed c. dq7 = complement of data written to dq7 figure 8. ac waveform for program operation product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 28 post office box 1443 ? houston, texas 772511443 write operation (continued) t ehdx t dveh t whwh1 t ehwh t wlel t eleh1 t ghel pa pa 555h t ehel t avel t elax 2aah 555h addresses ce oe we dq aah 55h a0h pd dq7 dout t avav notes: a. pa = address to be programmed b. pd = data to be programmed c. dq7 = complement of data written to dq7 figure 9. alternate ce -controlled write operation product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 29 post office box 1443 ? houston, texas 772511443 chip-erase operation yes no poll device status operation complete ? write bus cycle 555h /80h write bus cycle 2aah / 55h write bus cycle 555h / aah write bus cycle 555h /10h write bus cycle 2aah / 55h write bus cycle 555h / aah start end figure 10. chip-erase algorithm product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 30 post office box 1443 ? houston, texas 772511443 chip-erase operation (continued) dout=ffh dq7=0 10h 55h aah 80h t avwl t wlax va 555h 2aah 555h dq we oe ce 555h addresses t whdx t dvwh t whwl t ghwl t wheh t elwl t avav t wlwh1 t whwh3 notes: a. va = any valid address b. figure details the last four bus cycles in a six-bus-cycle operation. figure 11. ac waveform for chip-erase operation product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 31 post office box 1443 ? houston, texas 772511443 sector-erase operation yes no operation complete ? write bus cycle sector address / 30h dq3 = 0 ? yes yes no no load additional sectors ? poll device status write bus cycle 555h / aah write bus cycle 2aah / 55h write bus cycle 555h / 80h write bus cycle 2aah / 55h write bus cycle 555h/aah start end figure 12. sector-erase algorithm product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 32 post office box 1443 ? houston, texas 772511443 sector-erase operation (continued) dout=ffh dq7=0 30h 55h aah 80h t whwh2 sa sa 2aah 555h dq we oe ce 555h addresses t whdx t dvwh t whwl t wlwh1 t ghwl t wheh t elwl t wlax t avwl t avav notes: a. sa = sector address to be erased b. figure details the last four bus cycles in a six-bus-cycle operation. figure 13. ac waveform for sector-erase operation product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 33 post office box 1443 ? houston, texas 772511443 data-polling operation yes no read dq0 dq7 addr = va dq5 = 1 ? dq7 = data ? yes yes no no dq7 = data ? read dq0 dq7 addr = va start fail pass notes: a. polling status bits dq7 and dq5 may change asynchronously. read dq7 after dq5 changes states. b. va = program address for byte-programming = selected sector address for sector erase = any valid address for chip erase figure 14. data-polling algorithm product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 34 post office box 1443 ? houston, texas 772511443 data-polling operation (continued) dout dq7 dq7 dq7 din dq we oe ce ain ain ain addresses t ghqx t ghqz t whgl1 t glqv t glqv t elqv t avqv t elqv t axqx t avqv t whwh1, 2, or 3 notes: a. din = last command data written to the device b. dq7 = complement of data written to dq7 c. dout = valid data output d. ain = valid address for byte-program, sector-erase, or chip-erase operation figure 15. ac waveform for data-polling operation product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 35 post office box 1443 ? houston, texas 772511443 toggle-bit operation no yes read dq0 dq7 addr = va dq5 = 1 ? dq6 = toggle ? yes no no yes dq6 = toggle ? read dq0 dq7 read dq0 dq7 addr = va start fail pass note a: polling status bits dq6 and dq5 can change asynchronously. read dq6 after dq5 changes states. figure 16. toggle-bit algorithm product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 36 post office box 1443 ? houston, texas 772511443 toggle-bit operation (continued) dout dq6 = stop toggle dq6 = toggle dq6 = toggle dq6 = toggle din dq we oe ce ain addresses t whgl2 t glqv t elqv t glqv t elqv t avqv t whwh1, 2 or 3 notes: a. din = last command data written to the device b. dq6 = toggle bit output c. dout = valid data output d. ain = valid address for byte-program, sector-erase, or chip-erase operation figure 17. ac waveforms for toggle-bit operation product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 37 post office box 1443 ? houston, texas 772511443 sector-protect operation yes no select sector address a13 a19 x = 1 oe and a9 = v id, ce , a0, and a6 = v il , a1 = v ih a9 = v ih or v il write reset command protect additional sectors ? apply one 100- m s pulse ce , oe , a0, a6 = v il , a1 = v ih , a9 = v id read data data = 01h ? x = 25 ? yes no no x = x+1 sector protect failed yes start end figure 18. sector-protect algorithm product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 38 post office box 1443 ? houston, texas 772511443 sector-protect operation (continued) dout dq we oe v id ce a0 a1 a6 a9 v id a13 a19 sector address t avqv t glqv t hvt t wlwh2 t hvt t ghvwl t hvt sector address note a: dout = 00h if selected sector is not protected, 01h if the sector is protected figure 19. ac waveform for sector-protect operation product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 39 post office box 1443 ? houston, texas 772511443 sector-unprotect operation yes no protect all sectors x = 1 oe , a9 = v id, ce and a0 = v il , a6 and a1 = v ih a9 = v ih or v il write reset command last sector ? apply one 10-ms pulse ce , oe , a0 = v il , a6 and a1 = v ih , a9 = v id read data data = 00h ? x = 1000 ? yes yes no x = x+1 sector unprotect failed no select sector address next sector address start end figure 20. sector-unprotect algorithm product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 40 post office box 1443 ? houston, texas 772511443 sector-unprotect operation (continued) a13 a19 dout dq we oe ce a0 a1 a6 v id a9 v id sector address t avqv t glqv t wlwh3 t hvt t ghvwl t hvt t hvt note a: dout = 00h if selected sector is not protected, 01h if the sector is protected figure 21. ac waveform for sector-unprotect operation product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 41 post office box 1443 ? houston, texas 772511443 temporary sector-unprotect operation reset = v id (see note a) perform erase or program operations reset = v ih temporary sector- group-unprotect completed (see note b) start notes: a. all protected sectors unprotected b. all previously protected sectors are protected once again figure 22. temporary sector-unprotect algorithm ry / by we ce reset program or erase command sequence t vlht 12 v 5 v figure 23. temporary sector-unprotect timing diagram product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 42 post office box 1443 ? houston, texas 772511443 parameter measurement information ce we ry / by the rising edge of the last we signal entire programming or erase operations t busy figure 24. ry/ by timing diagram during program/erase operations product preview
tms29f008t, tms29f008b 1048576 by 8-bit flash memories smjs845a march 1997 revised october 1997 43 post office box 1443 ? houston, texas 772511443 mechanical data dcd (r-pdso-g**) plastic dual small-outline package a min 0.385 0.469 (11,90) (9,80) 48 40 40 21 0.004 (0,10) 0.012 (0,30) 0.037 (0,95) 0.041 (1,05) no. of pins ** 0.047 (1,20) max 0.402 (10,20) 0.476 (12,10) max 4073307/b 07/96 0.010 (25,00) nom seating plane 0.728 (18,50) 0.720 (18,30) 0.780 (19,80) 0.795 (20,20) 1 a 20 nom 0.006 (0,15) 0.028 (0,70) 0.020 (0,50) 0.004 (0,10) m 0.008 (0,21) 0.020 (0,50) 40 pin shown notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. product preview
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